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? 2005 microchip technology inc. ds21882c-page 1 mcp6241/2/4 features ? gain bandwidth product: 550 khz (typ.) ? supply current: i q = 50 a (typ.) ? supply voltage: 1.8v to 5.5v ? rail-to-rail input/output ? extended temperature range: -40c to +125c ? available in 5-pin sc-70 and sot-23 packages applications ? automotive ? portable equipment ? photodiode (transimpedance) amplifier ? analog filters ? notebooks and pdas ? battery-powered systems available tools ? spice macro models (at www.microchip.com) ?filterlab ? software (at www.microchip.com) typical application description the microchip technology inc. mcp6241/2/4 operational amplifiers (op amps) provide wide bandwidth for the quiescent current. the mcp6241/2/4 has a 550 khz gain bandwidth product (gbwp) and 68 (typ.) phase margin. this family operates from a single supply voltage as low as 1.8v, while drawing 50 a (typ.) quiescent current. in addition, the mcp6241/2/4 family supports rail-to-rail input and output swing, with a common mode input voltage range of v dd + 300 mv to v ss ? 300 mv. these op amps are designed in one of microchip?s advanced cmos processes. package types mcp6241 v out v in2 ? + v in1 r g2 r g1 r f r z v dd r x r y summing amplifier circuit 4 mcp6241 1 2 3 ? + 5 v dd v in ? v out v ss v in + sot-23-5 4 1 2 3 + 5 v dd v out v ss mcp6241r sot-23-5 4 1 2 3 ? + 5 v ss v in ? v out v dd v in + MCP6241U sc-70-5, sot-23-5 4 1 2 3 ? + 5 v dd v out v in + v ss v in ? v in + v in ? mcp6241 v ss v dd v out 1 2 3 4 8 7 6 5 ? + nc nc nc pdip, soic, msop mcp6242 pdip, soic, msop 1 2 3 4 8 7 6 5 - + - + v ina _ v ina + v ss v outa v outb v dd v inb _ v inb + mcp6244 v ina + v ina ? v ss 1 2 3 4 14 13 12 11 - v outa + - + v dd v outd v ind ? v ind + 10 9 8 5 6 7 v outb v inb ? v inb + v inc + v inc ? v outc + - - + pdip, soic, tssop 50 a, 550 khz rail-to-rail op amp
mcp6241/2/4 ds21882c-page 2 ? 2005 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings ? v dd ? v ss ........................................................................7.0v all inputs and outputs ................... v ss ? 0.3v to v dd + 0.3v difference input voltage ...................................... |v dd ? v ss | output short circuit current ..................................continuous current at input pins ....................................................2 ma current at output and supply pins ............................30 ma storage temperature.....................................-65c to +150c maximum junction temperature (t j ) .......................... +150c esd protection on all pins (hbm;mm) ............... 4 kv; 300v ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listi ngs of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics electrical characteristics : unless otherwise indicated, t a = +25c, v dd = +1.8v to +5.5v, v ss = gnd, v cm = v dd /2, r l = 100 k to v dd /2 and v out v dd /2. parameters sym min typ max units conditions input offset input offset voltage v os -5.0 ? +5.0 mv v cm = v ss extended temperature v os -7.0 ? +7.0 mv t a = -40c to +125c, v cm = v ss (note) input offset drift with temperature v os / t a ?3.0 ?v/ct a = -40c to +125c, v cm = v ss power supply rejection psrr ? 83 ? db v cm = v ss input bias current and impedance input bias current: i b ?1.0 ?pa at temperature i b ?20 ?pat a = +85c at temperature i b ? 1100 ? pa t a = +125c input offset current i os ?1.0 ?pa common mode input impedance z cm ?10 13 ||6 ? ||pf differential input impedance z diff ?10 13 ||3 ? ||pf common mode common mode input range v cmr v ss ? 0.3 ? v dd + 0.3 v common mode rejection ratio cmrr 60 75 ? db v cm = -0.3v to 5.3v, v dd = 5v open-loop gain dc open-loop gain (large signal) a ol 90 110 ? db v out = 0.3v to v dd ? 0.3v, v cm =v ss output maximum output voltage swing v ol , v oh v ss + 35 ? v dd ? 35 mv r l = 10 k , 0.5v output overdrive output short-circuit current i sc ?6 ?mav dd = 1.8v i sc ?23 ?mav dd = 5.5v power supply supply voltage v dd 1.8 ? 5.5 v quiescent current per amplifier i q 30 50 70 a i o = 0, v cm = v dd ? 0.5v note: the sc-70 package is only tested at +25c.
? 2005 microchip technology inc. ds21882c-page 3 mcp6241/2/4 ac electrical characteristics temperature characteristics electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +1.8 to 5.5v, v ss = gnd, v cm = v dd /2, v out v dd /2, r l = 10 k to v dd /2 and c l = 60 pf. parameters sym min typ max units conditions ac response gain bandwidth product gbwp ? 550 ? khz phase margin pm ? 68 ? g = +1 slew rate sr ? 0.30 ? v/s noise input noise voltage e ni ?10?v p-p f = 0.1 hz to 10 hz input noise voltage density e ni ?45?nv/ hz f = 1 khz input noise current density i ni ?0.6?fa/ hz f = 1 khz electrical characteristics: unless otherwise indicated, v dd = +1.8v to +5.5v and v ss = gnd. parameters sym min typ max units conditions temperature ranges extended temperature range t a -40 ? +125 c operating temperature range t a -40 ? +125 c (note) storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 5l-sc70 ja ? 331 ? c/w thermal resistance, 5l-sot-23 ja ? 256 ? c/w thermal resistance, 8l-msop ja ?206?c/w thermal resistance, 8l-pdip ja ?85?c/w thermal resistance, 8l-soic ja ?163?c/w thermal resistance, 14l-pdip ja ?70?c/w thermal resistance, 14l-soic ja ?120?c/w thermal resistance, 14l-tssop ja ?100?c/w note: the internal junction temperature (t j ) must not exceed the absolute maximum specification of +150c.
mcp6241/2/4 ds21882c-page 4 ? 2005 microchip technology inc. 2.0 typical performance curves note: unless otherwise indicated, t a = +25c, v dd = +1.8v to +5.5v, v ss = gnd, v cm = v dd /2, v out v dd /2, r l = 100 k to v dd /2 and c l = 60 pf. figure 2-1: input offset voltage. figure 2-2: psrr, cmrr vs. frequency. figure 2-3: input bias current at +85c. figure 2-4: cmrr, psrr vs. ambient temperature. figure 2-5: open-loop gain, phase vs. frequency. figure 2-6: input bias current at +125c. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% -5 -4 -3 -2 -1 0 1 2 3 4 5 input offset voltage (mv) percentage of occurrences 630 samples v cm = v ss 20 30 40 50 60 70 80 90 100 110 1.e+01 1.e+02 1.e+03 1.e+04 1.e+0 5 frequency (hz) psrr, cmrr (db) 10 1k 10k 100k 100 psrr+ psrr- cmrr 0% 5% 10% 15% 20% 25% 0 6 12 18 24 30 36 42 input bias current (pa) percentage of occurrences 180 samples v cm = v dd /2 t a = +85c 70 75 80 85 90 -50-25 0 255075100125 ambient temperature (c) cmrr, psrr (db) psrr (v cm = v ss ) cmrr (v cm = -0.3v to +5.3v, v dd = 5.0v) -20 0 20 40 60 80 100 120 1.e- 01 1.e+ 00 1.e+ 01 1.e+ 02 1.e+ 03 1.e+ 04 1.e+ 05 1.e+ 06 1.e+ 07 frequency (hz) open-loop gain (db) -210 -180 -150 -120 -90 -60 -30 0 open-loop phase () r l = 10.0 k : v cm = v dd /2 0.1 1 10 100 1k 10k 100k 1m 10m gain phase 0% 5% 10% 15% 20% 25% 30% 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 input bias current (na) percentage of occurrences 180 samples v cm = v dd /2 t a = +125c
? 2005 microchip technology inc. ds21882c-page 5 mcp6241/2/4 note: unless otherwise indicated, t a = +25c, v dd = +1.8v to +5.5v, v ss = gnd, v cm = v dd /2, v out v dd /2, r l = 100 k to v dd /2 and c l = 60 pf. figure 2-7: input noise voltage density vs. frequency. figure 2-8: input offset voltage vs. common mode input voltage at v dd = 1.8v. figure 2-9: input offset voltage vs. common mode input voltage at v dd = 5.5v. figure 2-10: input offset voltage drift. figure 2-11: input offset voltage vs. output voltage. figure 2-12: output short-circuit current vs. ambient temperature. 10 100 1,000 10,000 1.e-01 1.e+0 0 1.e+0 1 1.e+0 2 1.e+0 3 1.e+0 4 1.e+0 5 frequency (hz) input noise voltage density (nv/ ? hz) 0.1 100 1k 10k 100k 10 1 -300 -200 -100 0 100 200 300 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 common mode input voltage (v) input offset voltage (v) v dd = 1.8v t a = -40c t a = +25c t a = +85c t a = +125c -200 -100 0 100 200 300 400 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) input offset voltage (v) v dd = 5.5v t a = -40c t a = +25c t a = +85c t a = +125c 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 input offset voltage drift (v/c) percentage of occurrences 628 samples v cm = v ss t a = -40c to +125c 300 350 400 450 500 550 600 650 700 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 output voltage (v) input offset voltage (v) v dd = 1.8v v cm = v ss v dd = 5.5v -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 0.00.51.01.52.02.53.03.54.04.55.05. 5 power supply voltage (v) short circuit current (ma) t a = +125c t a = +85c t a = +25c t a = -40c +i sc -i sc
mcp6241/2/4 ds21882c-page 6 ? 2005 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = +1.8v to +5.5v, v ss = gnd, v cm = v dd /2, v out v dd /2, r l = 100 k to v dd /2 and c l = 60 pf. figure 2-13: slew rate vs. ambient temperature. figure 2-14: output voltage headroom vs. output current magnitude. figure 2-15: maximum output voltage swing vs. frequency. figure 2-16: small-signal, non-inverting pulse response. figure 2-17: large-signal, non-inverting pulse response. figure 2-18: quiescent current vs. power supply voltage. 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 -50 -25 0 25 50 75 100 125 ambient temperature (c) slew rate (v/s) falling edge rising edge v dd = 1.8v v dd = 5.5v 1 10 100 1,000 1.e-02 1.e-01 1.e+00 1.e+0 1 output current magnitude (a) output voltage headroom (mv) v dd ? v oh 10m 1m v ol ? v ss 100 10 0.1 1 10 1.e+03 1.e+04 1.e+05 1.e+0 6 frequency (hz) max. output voltage swing (v p-p ) v dd = 5.5v v dd = 1.8v 1k 10k 100k 1m time (1 s/div) output voltage (10 mv/div) g = +1 v/v r l = 10 k : 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 time (10 s/div) output voltage (v) v dd = 5.0v g = +1 v/v 0 10 20 30 40 50 60 70 80 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 power supply voltage (v) quiescent current per amplifier (a) v cm = 0.9v dd t a = +125c t a = +85c t a = +25c t a = -40c
? 2005 microchip technology inc. ds21882c-page 7 mcp6241/2/4 3.0 pin descriptions descriptions of the pins are listed in table 3-1 (single op amps) and table 3-2 (dual and quad op amps). table 3-1: pin function table for single op amps table 3-2: pin function table for dual and quad op amps 3.1 analog outputs the output pins are low-impedance voltage sources. 3.2 analog inputs the non-inverting and inverting inputs are high- impedance cmos inputs with low bias currents. 3.3 power supply (v ss and v dd ) the positive power supply (v dd ) is 1.8v to 5.5v higher than the negative power supply (v ss ). for normal operation, the other pins are between v ss and v dd . typically, these parts are used in a single-(positive) supply configuration. in this case, v ss is connected to ground and v dd is connected to the supply. v dd will need a local bypass capacitor (typically 0.01 f to 0.1 f) within 2 mm of the v dd pin. these parts can share a bulk capacitor (typically 1 f to 100 f) with other nearby analog parts; it needs to be within 100 mm of the v dd pin. mcp6241 (pdip, soic, msop) mcp6241 (sot-23-5) mcp6241r (sot-23-5) MCP6241U (sot-23-5) symbol description 6114v out analog output 2443v in ? inverting input 3331v in + non-inverting input 7525v dd positive power supply 4252v ss negative power supply 1, 5, 8 ? ? ? nc no internal connection mcp6242 mcp6244 symbol description 11v outa analog output (op amp a) 22v ina ? inverting input (op amp a) 33v ina + non-inverting input (op amp a) 84v dd positive power supply 55v inb + non-inverting input (op amp b) 66v inb ? inverting input (op amp b) 77v outb analog output (op amp b) ?8v outc analog output (op amp c) ?9v inc ? inverting input (op amp c) ?10v inc + non-inverting input (op amp c) 411v ss negative power supply ?12v ind + non-inverting input (op amp d) ?13v ind ? inverting input (op amp d) ?14v outd analog output (op amp d)
mcp6241/2/4 ds21882c-page 8 ? 2005 microchip technology inc. 4.0 application information the mcp6241/2/4 family of op amps is manufactured using microchip?s state-of-the-art cmos process and is specifically designed for low-power and general- purpose applications. the low supply voltage, low quiescent current and wide bandwidth makes the mcp6241/2/4 ideal for battery-powered applications. 4.1 rail-to-rail inputs the mcp6241/2/4 op amps are designed to prevent phase reversal when the input pins exceed the supply voltages. figure 4-1 shows the input voltage exceeding the supply voltage without any phase reversal. figure 4-1: the mcp6241/2/4 show no phase reversal. the input stage of the mcp6241/2/4 op amps use two differential input stages in parallel. one operates at low common mode input voltage (v cm ) and the other at high v cm . with this topology, the device operates with v cm up to 300 mv above v dd and 300 mv below v ss . the input offset voltage is measured at v cm =v ss ? 300 mv and v dd + 300 mv to ensure proper operation. input voltages that exceed the input voltage range (v ss ? 0.3v to v dd + 0.3v at 25c) can cause excessive current to flow into or out of the input pins. current beyond 2 ma can cause reliability problems. applications that exceed this rating must be externally limited with a resistor, as shown in figure 4-2. figure 4-2: input current-limiting resistor (r in ). 4.2 rail-to-rail output the output voltage range of the mcp6241/2/4 op amps is v dd ? 35 mv (max.) and v ss + 35 mv (min.) when r l =10k is connected to v dd /2 and v dd = 5.5v. refer to figure 2-14 for more information. 4.3 capacitive loads driving large capacitive loads can cause stability problems for voltage-feedback op amps. as the load capacitance increases, the feedback loop?s phase margin decreases and the closed-loop bandwidth is reduced. this produces gain peaking in the frequency response, with overshoot and ringing in the step response. a unity-gain buffer (g = +1) is the most sensitive to capacitive loads, but all gains show the same general behavior. when driving large capacitive loads with these op amps (e.g., > 70 pf when g = +1), a small series resistor at the output (r iso in figure 4-3) improves the feedback loop?s phase margin (stability) by making the output load resistive at higher frequencies. the bandwidth will be generally lower than the bandwidth with no capacitive load. figure 4-3: output resistor, r iso stabilizes large capacitive loads. figure 4-4 gives recommended r iso values for different capacitive loads and gains. the x-axis is the normalized load capacitance (c l /g n ), where g n is the circuit?s noise gain. for non-inverting gains, g n and the signal gain are equal. for inverting gains, g n is 1 + |signal gain| (e.g., ?1 v/v gives g n = +2 v/v). -1 0 1 2 3 4 5 6 time (1 ms/div) input, output voltage (v) v out v in v dd = 5.0v g = +2 v/v r in v ss minimum expected v in () ? 2 ma --------------------------------------------------------------------------- - r in maximum expected v in () v dd ? 2 ma ------------------------------------------------------------------------------ - v in r in v out mcp624x ? + v in r iso v out mcp624x c l ? +
? 2005 microchip technology inc. ds21882c-page 9 mcp6241/2/4 figure 4-4: recommended r iso values for capacitive loads. after selecting r iso for your circuit, double-check the resulting frequency response peaking and step response overshoot. evaluation on the bench and simulations with the mcp6241/2/4 spice macro model are very helpful. modify r iso ?s value until the response is reasonable. 4.4 supply bypass with this op amp, the power supply pin (v dd for single-supply) should have a local bypass capacitor (i.e., 0.01 f to 0.1 f) within 2 mm for good high- frequency performance. it can use a bulk capacitor (i.e., 1 f or larger) within 100 mm to provide large, slow currents. this bulk capacitor can be shared with other nearby analog parts. 4.5 unused op amps an unused op amp in a quad package (mcp6244) should be configured as shown in figure 4-5. both circuits prevent the output from toggling and causing crosstalk. circuit a can use any reference voltage between the supplies, provides a buffered dc voltage, and minimizes the supply current draw of the unused op amp. circuit b minimizes the number of components, but may draw a little more supply current for the unused op amp. figure 4-5: unused op amps. 4.6 pcb surface leakage in applications where low input bias current is critical, pcb (printed circuit board) surface leakage effects need to be considered. surface leakage is caused by humidity, dust or other contamination on the board. under low humidity conditions, a typical resistance between nearby traces is 10 12 . a 5v difference would cause 5 pa of current to flow, which is greater than the mcp6241/2/4 family?s bias current at 25c (1 pa, typ.). the easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). the guard ring is biased at the same voltage as the sensitive pin. an example of this type of layout is shown in figure 4-6. figure 4-6: example guard ring layout for inverting gain. 1. non-inverting gain and unity-gain buffer: a. connect the non-inverting pin (v in +) to the input with a wire that does not touch the pcb surface. b. connect the guard ring to the inverting input pin (v in ?). this biases the guard ring to the common mode input voltage. 2. inverting gain and transimpedance amplifiers (convert current to voltage, such as photo detectors): a. connect the guard ring to the non-inverting input pin (v in +). this biases the guard ring to the same reference voltage as the op amp (e.g., v dd /2 or ground). b. connect the inverting pin (v in ?) to the input with a wire that does not touch the pcb surface. 1.e+02 1.e+03 1.e+04 1.e+01 1.e+02 1.e+03 1.e+04 normalized load capacitance; c l /g n (f) recommended r iso ( : ) 10p 100p 1n 10n 10k 1k 100 g n = +1 v/v g n t +2 v/v v dd v dd v dd ? mcp6244 (a) ? mcp6244 (b) guard ring v ss v in -v in +
mcp6241/2/4 ds21882c-page 10 ? 2005 microchip technology inc. 4.7 application circuits 4.7.1 matching the impedance at the inputs to minimize the effect of offset voltage in an amplifier circuit, the impedances at the inverting and non- inverting inputs need to be matched. this is done by choosing the circuit resistor values so that the total resistance at each input is the same. figure 4-7 shows a summing amplifier circuit. figure 4-7: summing amplifier circuit. to match the inputs, set all voltage sources to ground and calculate the total resistance at the input nodes. in this summing amplifier circuit, the resistance at the inverting input is calculated by setting v in1 , v in2 and v out to ground. in this case, r g1 , r g2 and r f are in parallel. the total resistance at the inverting input is: at the non-inverting input, v dd is the only voltage source. when v dd is set to ground, both r x and r y are in parallel. the total resistance at the non-inverting input is: to minimize offset voltage and increase circuit accuracy, the resistor values need to meet the condition: 4.7.2 compensating for the parasitic capacitance in analog circuit design, the pcb parasitic capacitance can compromise the circuit behavior; figure 4-8 shows a typical scenario. if the input of an amplifier sees parasitic capacitance of several picofarad (c para , which includes the common mode capacitance of 6 pf, typical) and large r f and r g , the frequency response of the circuit will include a zero. this parasitic zero introduces gain peaking and can cause circuit instability. figure 4-8: effect of parasitic capacitance at the input. one solution is to use smaller resistor values to push the zero to a higher frequency. another solution is to compensate by introducing a pole at the point at which the zero occurs. this can be done by adding c f in parallel with the feedback resistor (r f ). c f needs to be selected so that the ratio c para :c f is equal to the ratio of r f :r g . mcp624x v out v in2 ? + v in1 r g2 r g1 r f r z v dd r x r y r vin ? 1 1 r g1 --------- 1 r g2 --------- 1 r f ------ ++ ?? ?? --------------------------------------------- = where: r vin ? = total resistance at the inverting input r vin + 1 1 r x ------ 1 r y ----- - + ?? ?? ------------------------- r z + = where: r vin + = total resistance at the inverting input r vin + r vin ? = v out c f v dc + ? v ac r g r f c para c f c para r g r f ------ - ? = mcp624x
? 2005 microchip technology inc. ds21882c-page 11 mcp6241/2/4 5.0 design tools microchip provides the basic design tools needed for the mcp6241/2/4 family of op amps. 5.1 spice macro model the latest spice macro model for the mcp6241/2/4 op amps is available on our web site at www.microchip.com. this model is intended to be an initial design tool that works well in the op amp?s linear region of operation at room temperature. see the macro model file for information on its capabilities. bench testing is a very important part of any design and cannot be replaced with simulations. also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 filterlab ? software microchip?s filterlab software is an innovative tool that simplifies analog active-filter (using op amps) design. available at no cost from our web site at www.microchip.com, the filterlab design tool provides full schematic diagrams of the filter circuit with component values. it also outputs the filter circuit in spice format, which can be used with the macro model to simulate actual filter performance.
mcp6241/2/4 ds21882c-page 12 ? 2005 microchip technology inc. 6.0 packaging information 6.1 package marking information 1 23 5 4 5-lead sot-23 example: xxnn 1 23 5 4 bq25 device code mcp6241 bqnn mcp6241 r brnn mcp6241 u bsnn note: applies to 5-lead sot-23. xxxxxxxx xxxxxnnn yyww 8-lead pdip (300 mil) example : 8-lead soic (150 mil) example : xxxxxxxx xxxxyyww nnn mcp6242 e/p ^^256 0546 mcp6242e sn^^ 0546 256 8-lead msop example : xxxxxx ywwnnn 6242e 546256 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 3 e 3 e 5-lead sc-70 (MCP6241U only) example: xxn (front) yww (back) at2 (front) 546 (back) xxnn or at25 or
? 2005 microchip technology inc. ds21882c-page 13 mcp6241/2/4 package marking information (continued) 14-lead pdip (300 mil) ( mcp6244 )example : 14-lead tssop ( mcp6244 ) example : 14-lead soic (150 mil) ( mcp6244 ) example: xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn xxxxxxxxxx yywwnnn xxxxxxxx yyww nnn mcp6244 0546256 6244e 0546 256 xxxxxxxxxx mcp6244 0546256 e/p ^^ e/sl^^ 3 e 3 e
mcp6241/2/4 ds21882c-page 14 ? 2005 microchip technology inc. 5-lead plastic small outline transistor package (lt) (sc-70) 0.30 0.15 .012 .006 b l e ad width 0.18 0.10 .007 .004 c l e ad thickn e ss 0.30 0.10 .012 .004 l foot l e ngth 2.20 1.80 .087 .071 d ov e rall l e ngth 1.35 1.15 .053 .045 e1 mold e d packag e width 2.40 1.80 .094 .071 e ov e rall width 0.10 0.00 .004 .000 a1 standoff 1.00 0.80 .039 .031 a2 mold e d packag e thickn e ss 1.10 0.80 .043 .031 a ov e rall h e ight 0.65 (bsc) .026 (bsc) p pitch 5 5 n numb e r of pins max nom min max nom min dim e nsion limits millimeters* inches units e xc ee d .005" (0.127mm) p e r sid e . dim e nsions d and e1 do not includ e mold flash or protrusions. mold flash or protrusions shall not not e s: jeita (eiaj) standard: sc-70 drawing no. c04-061 *controlling param e t e r l e1 e c d 1 b p a2 a1 a q1 top of mold e d pkg to l e ad should e r q1 .004 .016 0.10 0.40 n
? 2005 microchip technology inc. ds21882c-page 15 mcp6241/2/4 5-lead plastic small outline transistor (ot) (sot23) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.50 0.43 0.35 .020 .017 .014 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 10 5 0 10 5 0 foot angle 0.55 0.45 0.35 .022 .018 .014 l foot length 3.10 2.95 2.80 .122 .116 .110 d overall length 1.75 1.63 1.50 .069 .064 .059 e1 molded package width 3.00 2.80 2.60 .118 .110 .102 e overall width 0.15 0.08 0.00 .006 .003 .000 a1 standoff 1.30 1.10 0.90 .051 .043 .035 a2 molded package thickness 1.45 1.18 0.90 .057 .046 .035 a overall height 1.90 .075 p1 outside lead pitch (basic) 0.95 .038 p pitch 5 5 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 p d b n e e1 l c a2 a a1 p1 exceed .005" (0.127mm) per side. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not notes: eiaj equivalent: sc-74a drawing no. c04-091 *controlling parameter
mcp6241/2/4 ds21882c-page 16 ? 2005 microchip technology inc. 8-lead plastic micro small outline package (ms) (msop) d a a1 l c (f) a2 e1 e p b n 1 2 dim e nsions d and e1 do not includ e mold flash or protrusions. mold flash or protrusions shall not .037 ref f footprint (r e f e r e nc e ) e xc ee d .010" (0.254mm) p e r sid e . not e s: drawing no. c04-111 *controlling param e t e r mold draft angl e top mold draft angl e bottom foot angl e l e ad width l e ad thickn e ss c b .003 .009 .006 .012 dim e nsion limits ov e rall h e ight mold e d packag e thickn e ss mold e d packag e width ov e rall l e ngth foot l e ngth standoff ov e rall width numb e r of pins pitch a l e1 d a1 e a2 .016 .024 .118 bsc .118 bsc .000 .030 .193 typ. .033 min p n units .026 bsc nom 8 inches 0.95 ref - - .009 .016 0.08 0.22 0 0.23 0.40 8 millimeters* 0.65 bsc 0.85 3.00 bsc 3.00 bsc 0.60 4.90 bsc .043 .031 .037 .006 0.40 0.00 0.75 min max nom 1.10 0.80 0.15 0.95 max 8 -- - 15 5 - 15 5 - jedec equival e nt: mo-187 0 - 8 5 5 - - 15 15 - - - -
? 2005 microchip technology inc. ds21882c-page 17 mcp6241/2/4 8-lead plastic dual in-line (p) ? 300 mil (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010? (0.254mm) per side. significant characteristic
mcp6241/2/4 ds21882c-page 18 ? 2005 microchip technology inc. 8-lead plastic small outline (sn) ? narrow, 150 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n p b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic
? 2005 microchip technology inc. ds21882c-page 19 mcp6241/2/4 14-lead plastic dual in-line (p) ? 300 mil (pdip) e1 n d 1 2 eb e c a a1 b b1 l a2 p units inches* millimeters dimension limits min nom max min nom max number of pins n 14 14 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .740 .750 .760 18.80 19.05 19.30 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 5 10 15 5 10 15 5 10 15 5 10 15 mold draft angle bottom * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-005 significant characteristic
mcp6241/2/4 ds21882c-page 20 ? 2005 microchip technology inc. 14-lead plastic small outline (sl) ? narrow, 150 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 8.81 8.69 8.56 .347 .342 .337 d overall length 3.99 3.90 3.81 .157 .154 .150 e1 molded package width 6.20 5.99 5.79 .244 .236 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-065 significant characteristic
? 2005 microchip technology inc. ds21882c-page 21 mcp6241/2/4 14-lead plastic thin shrink small outline (st) ? 4.4 mm (tssop) 8 4 0 8 4 0 foot angle 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.30 0.25 0.19 .012 .010 .007 b1 lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 0.70 0.60 0.50 .028 .024 .020 l foot length 5.10 5.00 4.90 .201 .197 .193 d molded package length 4.50 4.40 4.30 .177 .173 .169 e1 molded package width 6.50 6.38 6.25 .256 .251 .246 e overall width 0.15 0.10 0.05 .006 .004 .002 a1 standoff 0.95 0.90 0.85 .037 .035 .033 a2 molded package thickness 1.10 .043 a overall height 0.65 .026 p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters* inches units l c 2 1 d n b p e1 e a2 a1 a * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005? (0.127mm) per side. jedec equivalent: mo-153 drawing no. c04-087 significant characteristic
mcp6241/2/4 ds21882c-page 22 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds21882c-page 23 mcp6241/2/4 appendix a: revision history revision c (march 2005) the following is the list of modifications: 1. added the mcp6244 quad op amp. 2. re-compensated parts. specifications that change are: gain bandwidth product (bwp) and phase margin (pm) in ac electrical characteristics table. 3. corrected plots in section 2.0 ?typical perfor- mance curves? . 4. added section 3.0 ?pin descriptions? . 5. added new sc-70 package markings. added pdip-14, soic-14, and tssop-14 packages and corrected package marking information ( section 6.0 ?packaging information? ). 6. added appendix a: ?revision history? . revision b (august 2004) revision a (march 2004) ? original release of this document.
mcp6241/2/4 ds21882c-page 24 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds21882c-page 25 mcp6241/2/4 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp6241: single op amp (msop, pdip, soic) mcp6241t: single op amp (tape and reel) (msop, soic, sot-23) mcp6241rt: single op amp (tape and reel) (sot-23) MCP6241Ut: single op amp (tape and reel) (sc-70, sot-23) mcp6242: dual op amp mcp6242t: dual op amp (tape and reel) (msop, soic) mcp6244: quad op amp mcp6244t: quad op amp (tape and reel) (soic, tssop) temperature range: e = -40c to +125c package: lt = plastic package (sc-70), 5-lead (MCP6241U only) ms = plastic micro small outline (msop), 8-lead p = plastic dip (300 mil body), 8-lead, 14-lead ot = plastic small outline transistor (sot-23), 5-lead (mcp6241, mcp6241r, MCP6241U) sn = plastic soic (150 mil body), 8-lead sl = plastic soic (150 mil body), 14-lead st = plastic tssop (4.4 mil body), 14-lead part no. - x /xx package temperature range device examples: a) mcp6241-e/sn: extended temp., 8ld soic package. b) mcp6241-e/ms: extended temp., 8ld msop package. c) mcp6241-e/p: extended temp., 8ld pdip package. d) mcp6241rt-e/ot: tape and reel, extended temp., 5ld sot-23 package e) MCP6241Ut-e/ot: tape and reel, extended temp., 5ld sot-23 package. f) MCP6241Ut-e/lt: tape and reel, extended temp., 5ld sc-70 package. a) mcp6242-e/sn: extended temp., 8ld soic package. b) mcp6242-e/ms: extended temp., 8ld msop package. c) mcp6242-e/p: extended temp., 8ld pdip package. d) mcp6242t-e/sn: tape and reel, extended temp., 8ld soic package. a) mcp6244-e/p: extended temp., 14ld pdip package. b) mcp6244-e/sl: extended temp., 14ld soic package. c) mcp6244-e/st: extended temp., 14ld tssop package. d) mcp6244t-e/sl: tape and reel, extended temp., 14ld soic package. e) mcp6244t-e/st: tape and reel, extended temp., 14ld tssop package. x tape and reel alternate pinout and/or
mcp6241/2/4 ds21882c-page 26 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds21882c-page 27 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. microchip makes no representations or war- ranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratable memory, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, mpasm, mplib, mplink, mpsim, pickit, picdem, picd em.net, piclab, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance and wiperlock are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2005, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outsi de the operating specifications c ontained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted wo rk, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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